Patent Prosecution, Patent Strategy, Patent Portfolio Analysis, Litigation Support, Due Diligence in Patent & IP Acquisitions, Expert Patent Analysis, Corporate Patent Practice & Law Firm Patent Prosecution


  •  Invented over 30 issued US patents
  • Founded & led technology startup through successful acquisition by Silicon Valley company
  •  IBM experience in patent development, technical, leadership, and marketing roles
  • Licensed to practice before the US Patent Office – Patent Agent
  • Authored or co-authored 2 books and over 20 papers
  •  Ph.D. in electrical and computer engineering & Masters in Engineering Management education, both from Dartmouth


 Professional Experience:

ADAMS INTELLEX, PLC (New England) - 2008-Present 

Founder / Principal

  • Draft and file provisional and utility patent applications (both US and international PCT applications). Conduct inventor interviews to glean key inventive concepts. Perform examiner interviews to facilitate patent prosecution. Draft office action responses identifying key differences from prior art to eliminate examiner concerns about anticipation and obviousness. Provide direction and instruction for foreign counsel. Recommend and confer with inventors to determine filing of continuations, divisionals, continuation-in-part patent applications, and request for continued examinations.
  • Provide expert patent analysis in litigation support, doing analysis of patents, prior art, and infringement arguments.


MAGMA DESIGN AUTOMATION, INC. (San Jose, CA) - 2003-2008

Director of IP Strategy (2006-2008)

  • Exponentially grew the patent portfolio across all areas of R&D as company more than doubled in size. Enlarged patent portfolio from a very small number to being industry leader competitive .
  • Enhanced patent portfolio through organic growth. Taught patenting across globe at company locations including visits to multiple sites in both India and China. Extracted patent concepts from developers. Drafted patent applications & office action amendments. Ensured protection before trade show announcements.
  • Increased patent portfolio through acquisition. Analyzed targets and determined value of patents & applications. Performed due diligence & drove perfecting of patent ownership.
  • Defined patent strategy. Selected concepts to pursue for patenting and to file internationally. Oversaw company’s entire patent portfolio.
  • Managed multiple outside patent counsel firms. Selected firm and specific attorney/agent for each application. Selectively filed provisionals and utilities. Controlled budget & negotiated costs.
  • Provided litigation support throughout major & minor corporate law suits. Identified & vetted expert analysts. Analyzed technology for prior art discovery.


Director of Product Development (2003-2006)

  • Managed design-for-test product development team. Recruited and coached technical contributors. Drove technical strategy for product line. 



Founder & President

  • Managed entrepreneurial startup from the beginning. Led PDAT through successful and profitable acquisition by Magma.  Developed new technology and pursued patent protection. Defined product specification and led team.  Marketed on-chip self-test concepts to semiconductor design houses.  Patent-portfolio analysis performed for venture capital clientele



Senior Engineer (2000-2002) (progressively greater responsibility/job titles over preceding time)

  • Recruited patent ideas from inventors across 400+ person multi-site development group. Led invention disclosure analysis teams for both hardware and software concepts. Developed numerous patentable concepts. Invented over 30 issued patents for these concepts. Initiated advanced technology development. Provided marketing & sales leadership for a product line.



  • Doctor of Philosophy in Electrical & Computer Engineering, Dartmouth College, Thayer School of Engineering, 1998
  • Master of Engineering Management (includes cross-section of MBA curriculum taught by Tuck School of Business faculty), Dartmouth College, Thayer School of Engineering, 1998
  • Master of Science in computer engineering, Dartmouth College, Thayer School of Engineering, 1996
  • Bachelor of Science in Electrical Engineering, University of Rhode Island, 1982


Honors, Activities, Memberships:

  • American Intellectual Property Law Association (AIPLA)
  • Boston Patent Law Association (BPLA)
  • Institute of Electrical and Electronic Engineers (IEEE)
  • Program committee member & paper reviewer for multiple conferences & workshops
  • Eighth Invention Plateau while at IBM
  • Distinguished Fellow while at Dartmouth, Thayer School

Books (authored or co-authored):

  • High Performance Memory Testing: Design Principles, Fault modeling, and Self-Test, R.D. Adams, Kluwer 2002 
  • Advances in Electronic Testing: Challenges and Methodologies, ed. D. Gizopoulos, (authored chapter on Embedded Memory Testing), Springer 2005


Patents (Over 30 Patents Issued):

  • “Testing of ECC memories,” U.S. Pat. No. 7,308,621, Dec. 11, 2007
  • “Asynchronous control of memory self test,” U.S. Pat. No. 7,203,873, Apr. 10, 2007
  • “Programmable multi-port memory BIST with compact microcode,” U.S. Pat. No. 7,168,005, Jan. 23, 2007
  • “Optimized ECC/redundancy fault recovery,” U.S. Pat. No. 7,149,941, Dec. 12, 2006
  • Method and apparatus for testing multi-port memories,” U.S. Pat. No. 7,032,144, Apr. 18, 2006
  • Two-dimensional redundancy calculation,” U.S. Pat. No. 7,003,704, Feb. 21, 2006
  • Built-in self test system and method for two-dimensional memory redundancy allocation,” U.S. Pat. No. 6,907,554, June 14, 2005
  • System initialization of microcode-based memory built-in self-test,” U.S. Pat. No. 6,874,111, Mar. 29, 2005
  • Built-in self test system and method for two-dimensional memory redundancy allocation,” U.S. Pat. No. 6,907,554, Nov. 11, 2004
  • Method and apparatus for testing memory cells for data retention faults,” U.S. Pat. No. 6,681,350, Jan. 20, 2004
  • Programmable memory built-in self-test combining microcode and finite state machine self-test,” U.S. Pat. No. 6,651,201, Nov. 18, 2003
  • Method and apparatus for testing multiport memories,” U.S. Pat. No. 6,557,127, Apr. 29, 2003
  • Testing method for dynamic logic keeper device,” U.S. Pat. No. 6,269,461, July 31, 2001
  • Fault identification by voltage potential signature,” U.S. Pat. No. 6,252,417, June 26, 2001
  • Semiconductor memory device having resistive bitline contact testing,” U.S. Pat. No. 6,208,572, Mar. 27, 2001
  • Method and apparatus for testing dynamic logic using an improved reset pulse,” U.S. Pat. No. 6,181,155, Jan. 30, 2001
  • On-chip test circuit for evaluating an on-chip signal using an external test signal,” U.S. Pat. No. 6,163,862, Dec. 19, 2000
  • Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure,” U.S. Pat. No. 5,912,901, June 15, 1999
  • Testing associative memory,” U.S. Pat. No. 5,802,070, Sept. 1, 1998
  • Memory array built-in self-test circuit for testing multi-port memory arrays,” U.S. Pat. No. 5,796,745, Aug. 18, 1998
  • Dynamic dielectric protection circuit for a receiver,” U.S. Pat. No. 5,793,592, Aug. 11, 1998
  • Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor,” U.S.Pat. No. 5,790,564, Aug. 4, 1998
  • Test coverage of embedded memories on semiconductor substrates,” U.S. Pat. No. 5,784,323, July 21, 1998
  • Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor,” U.S.Pat. No. 5,771,242, June 23, 1998
  • Method and apparatus to determine erroneous value in memory cells using data compression,” U.S. Pat. No. 5,761,213, June 2, 1998
  • Rapid compare of two binary numbers,” U.S. Pat. No. 5,745,498, Apr. 28, 1998
  • Using one memory to supply addresses to an associated memory during testing,” U.S. Pat. No. 5,563,833, October 8, 1996, Pat. No. 5,740,098, Apr. 14, 1998
  • High speed greater than or equal to compare circuit,” U.S. Pat. No. 5,592,142, Jan. 7, 1997
  • BIST Tester for multiple memories,” U.S. Pat. No. 5,535,164, July 9, 1996
  • Module level electronic redundancy,” U.S. Pat. No. 5,313,424, May 17, 1994
  • CMOS Off-chip driver circuits,” U.S. Pat. No. 4,782,250, Nov. 1, 1988

Papers, Tutorials, & Conference Presentations (over 40):

  • “Judicious Patenting: The Lifeblood of Technology Entrepreneurship,” panelist, IEEE North Atlantic Test Workshop, May 2010
  • “Process Variation: The Line Blurs,” panelist, IEEE North Atlantic Test Workshop, May 2009
  • Embedded Memory Diagnosis and Characterization session chairInternational Test Conference, Oct. 2008 (other session chair occurrences too numerous to mention and not included below)
  • Memory Test and Self-Test for Deep-Submicron Technologies,” IEEE Asian Test Symposium Tutorial, Nov. 2006
  • Memory Test and Self-Test for Deep-Submicron Technologies,” IEEE Latin American Test Workshop Tutorial, Mar. 2006
  • “Embedded SRAM Design for Testability” Forum Presentation, IEEE International Solid-State Circuits Conference, Feb. 2006
  • Memory Test and Self-Test for Deep-Submicron Technologies,” International Test Conference Tutorial, Nov. 2005
  • “Process Variations in the Nanometer Era,” panelist, IEEE International Test Synthesis Workshop, Apr. 2005
  • Memory Test and Self-Test for Deep-Submicron Technologies,” International Test Conference Tutorial, Oct. 2004
  • An Integrated Memory Self Test and EDA Solution,” IEEE Memory Technology, Design, and Test Workshop, Aug. 2004, pp. 92-5
  • Memory Redundancy and Built-In Self Repair,” IEEE Memory Technology, Design, and Test Workshop Embedded Tutorial, Aug. 2004
  • Memory Test and Self-Test for Deep-Submicron Technologies,” VLSI Test Symposium Tutorial, Apr. 2004
  • “Practical Memory BIST Analysis and Implementation,” International Test Conference Tutorial, Sept. 2003
  • “Optimizing Memory Self Test for Defects,” International Test Conference Tutorial, Oct. 2002
  • “Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch,” IEEE Memory Technology, Design, and Test Workshop 2002, pp. 83-7
  • “Bitline Contacts in High-Density SRAMS: Design for Testability and Stressability,” International Test Conference 2001, pp. 776-82
  • “Defect Analysis And A New Fault Model For Multi-Port SRAMs,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 2001
  • “Defect Analysis and Realistic Fault Model Extensions for Multi-port SRAMs,” IEEE North Atlantic Test Workshop, May 2001
  • “Memory Self Test Utilizing Design Factors,” International Test Conference Tutorial, Oct. 2000
  • “Self Test Architecture for Testing Complex Memory Structures,” International Test Conference 2000, pp. 547-56
  • “Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories,” IEEE Memory Technology, Design, and Test Workshop 2000, pp. 119-124
  • “Test Strategy and March Test Algorithms for Testing Complex Memory Structures,” IEEE North Atlantic Test Workshop, May 2000, pp. 38-43
  • “Memory Testing and SOI Technology,” IEEE North Atlantic Test Workshop Tutorial, May 2000
  • Silicon On Insulator Technology Impacts on SRAM Testing,” VLSI Test Symposium 2000, pp. 43-47
  • “System On a Chip Testing,” Custom Integrated Circuits Symposium Tutorial, May 1999
  • “The Limits of Digital Testing for Dynamic Circuits,” VLSI Test Symposium 1999, pp. 28-32
  • “Quad DCVS Dynamic Logic Fault Modeling and Testing,” International Test Conference 1998, pp. 356-62
  • “Fault Modeling Analysis Methodology Illustrated with a Dynamic Logic Circuit,” IEEE North Atlantic Test Workshop 1998, pp. 1-5
  • “Toward the One-Gigahertz PC: The Design and Test challenges,” Distinguished Fellow Lecture, Dartmouth/Thayer, May 21, 1998
  • “Testing Advanced Dynamic Logic,” VLSI Test Symposium Tutorial, Apr. 1998
  • “Quad DCVS: A Dynamic Differential Logic Family with Precharge Low and High I/O,” Second IEEE International Caracas Conference on Devices, Circuits, and Systems 1998, pp. 142-5
  • “A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal,” International Test Conference 1997, pp. 217-25
  • “False Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs,” IEEE Memory Design, Technology, and Test Workshop 1997, pp. 27-32
  • “A 5 nanosecond Store Barrier Cache with Dynamic Prediction of Load / Store Conflicts in Superscalar Processors,” IEEE International Solid-State Circuits Conference 1997, pp. 414-5
  • “Analysis of a Deceptive Destructive Read Memory Fault Model and Recommended Testing,”  IEEE North Atlantic Test Workshop, May 30, 1996
  • “Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem,” International Test Conference 1995, pp. 33-44
  • “A 370-M Hz Memory Built-In Self-Test State Machine,” European Design and Test Conference 1995, pp. 139-41
  • “A 576K 3.5-ns Access BiCMOS ECL Static RAM with Array Built-In Self-Test,” IEEE J. Solid-State Circuits, Vol. 27, No 4, Apr. 1992, pp. 649-56
  • “A Flexible and Adaptable SRAM Array Built-In Self-Test Design,” IEEE Design for Testability Workshop Apr. 1992, presentation
  • “A 576K 3.5 ns Access BiCMOS ECL Static RAM with Array Built-In Self-Test,” VLSI Circuits Symposium 1991
  • “An 11-ns 8Kx18 CMOS Static RAM with 0.5-um Devices,” IEEE J. Solid-State Circuits, Vol. 23, No. 5, Oct. 1988, pp. 1095-1103
  • “An 11-ns 8Kx18 CMOS Static RAM,” IEEE International Solid-State Circuits Conference 1988, pp. 242-3



Adams Intellex, PLC - Patent Strategy / Patent Prosecution